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NXP Semiconductors
LPC11C12/C14
Table 14.
Dynamic characteristics of SPI pins in SPI mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
t DH
data hold time
in SPI mode
[3][4]
3 × T cy(PCLK) + 4
-
-
ns
t v(Q)
t h(Q)
data output valid time in SPI mode
data output hold time in SPI mode
[3][4]
[3][4]
-
-
-
-
3 × T cy(PCLK) + 11
2 × T cy(PCLK) + 5
ns
ns
[1]
[2]
[3]
[4]
T cy(clk) = (SSPCLKDIV × (1 + SCR) × CPSDVSR) / f main . The clock cycle time derived from the SPI bit rate T cy(clk) is a function of the
main clock frequency f main , the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),
and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).
T amb = ? 40 ° C to 85 ° C.
T cy(clk) = 12 × T cy(PCLK) .
T amb = 25 ° C; for normal voltage supply range: V DD = 3.3 V.
SCK (CPOL = 0)
SCK (CPOL = 1)
T cy(clk)
t v(Q)
t clk(H)
t clk(L)
t h(Q)
MOSI
DATA VALID
DATA VALID
t DS
t DH
CPHA = 1
MISO
MOSI
DATA VALID
t v(Q)
DATA VALID
DATA VALID
DATA VALID
t h(Q)
t DS
t DH
CPHA = 0
MISO
DATA VALID
DATA VALID
002aae829
Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1.
Fig 20. SPI master timing in SPI mode
LPC11C12_C14_0
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 00.05 — 23 April 2010
? NXP B.V. 2010. All rights reserved.
38 of 49
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